Job description
Summary
Key Qualifications
- RTL design using Verilog or SystemVerilog, assertion writing
- Design of state machines, data paths, arbitration and clock domain crossing logic
- Logic synthesis, timing constraints
- Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
- Prior experience in DDR PHY design and mixed-signal environment is a plus