Job description
Title: FPGA Verification Engineer
Location: Cedar Rapids, Iowa - REMOTE
Duration: Fulltime
JD:
Extensive experience with System Verilog & UVM Methodology (SV / UVM)
Test Bench architecture, Test Bench Troubleshooting, Test Case writing & Execution
Video/Image Processing Project Experience
Adherence to avionics products, process & documentation
DO-254 Process knowledge is desired
Remote / Open for Occasional Travel.
Job Type: Full-time
Salary: $100,000.00 - $130,000.00 per year
Benefits:
- 401(k)
- Dental insurance
- Health insurance
- Paid time off
- Relocation assistance
- Vision insurance
Schedule:
- Monday to Friday
Experience:
- FPGA: 2 years (Preferred)
- Firmware Verification: 2 years (Preferred)
- System Verilog: 2 years (Preferred)
- UVM: 2 years (Preferred)
Work Location: Remote
Speak with the employer
+91 6304874549