machine learning engineer Sunnyvale, CA
Job description
Minimum qualifications:
- Bachelor's degree in Electrical/Computer engineering, Computer Science, or equivalent practical experience
- 4 years of experience in RTL logic design and integration using SystemVerilog or similar HDL
- Experience in automation flow with EDA tools using Python, Perl, or TCL
- Experience using one or more RTL sign-off flows (e.g., CDC, RDC, Lint, Power Intent, LEC)
Preferred qualifications:
- Master's degree or PhD in Electrical/Computer engineering, Computer Science, or equivalent practical experience
- 5 years of experience with ASIC design, integrating SoCs with multiple voltage rails
- Expertise running industry-standard CDC tools (e.g., Spyglass CDC or Meridian CDC)
- Expertise running industry-standard Lint tools (e.g., Spyglass Lint or Ascent Lint)
- Expertise running industry-standard Power Intent tools (e.g., VC LP or Conformal LP)
- Expertise running industry-standard LEC tools (e.g., Formality or Conformal LEC)
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $124,000-$182,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Develop and maintain sign-off RTL integration sign-off flows (e.g., CDC, RDC, Lint, Power Intent, and LEC).
- Define chip-wide methodologies for the above sign-off flows.
- Drive RTL sign-off closure at the full-chip level.
