design engineer Sunnyvale, CA
Job description
Minimum qualifications:
- Bachelor's degree in Electrical/Computer engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in ASIC design.
- Experience in a scripting language (e.g., Python, Perl, or TCL).
Preferred qualifications:
- Master's degree in Electrical/Computer engineering, Computer Science, or equivalent practical experience.
- Knowledge of high performance and low power design techniques.
- Knowledge of FPGA, emulation platforms, and SoC architecture.
- Knowledge of assertion-based design verification.
- Domain knowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators and/or memory hierarchies.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $105,000-$152,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Define the block level design document (e.g., interface protocol, block diagram, transaction flow, and pipeline).
- Perform RTL development (i.e., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and FPGA/emulation/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SoC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
