verification engineer Menlo Park, CA
Job description
Role - Design Verification Lead
Location - Menlo Park, CA (onsite)
Duration - Fulltime
Keywords to search:
SV, UVM, Verification, DSP, ASIC, SRAM, DRAM, GPU, UVM,IP, SoC.
JOB DETAIL
- The candidate will be part of silicon design team chartered with delivering IP and Subsystem designs to multiple server SOCs
- 10+ years experience
- At least 5 years in UVM
- creating testbench from scratch by hand on at least one complex projects.
* Passionate about modern AIs like ChatGPT, and willing to learn about them on the job.
* Interact closely with the architecture and design teams, influencing product definition, implementation and validation. Create, define and develop system validation environment and test suites.- Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests.
*Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
* He should be able to Manage and Co-ordinate with the Off-shore team members.
Job Type: Full-time
Salary: $140,054.99 - $160,000.00 per year
Schedule:
- 8 hour shift
Ability to commute/relocate:
- Menlo Park, CA: Reliably commute or planning to relocate before starting work (Required)
Experience:
- Design Verification Lead: 10 years (Preferred)
- UVM: 5 years (Preferred)
- modern AIs like ChatGPT, and willing to learn: 5 years (Preferred)
- SV, Verification, DSP, ASIC, SRAM, DRAM, GPU, UVM,IP, SoC: 10 years (Preferred)
Work Location: In person
