verification engineer Sunnyvale, CA
Job description
ASIC Verification Engineer
Responsibilities:
You will utilize the latest verification methodologies like UVM to develop complex verification suites to verify advanced networking chips.
You will start with a functional specification of a module and produce a detailed test plan to verify the module.
You will write functional models for the module using System Verilog/C/C++ for architectural validation.
You will build the module level test bench using System Verilog/UVM
You will write tests according to the test plan to thoroughly verify the module. You will be responsible for making sure your module is fully functional.
You will incorporate functional coverage to ensure all functionality is tested.
You will work closely with logic designers to resolve bugs, with SW engineers to assist in driver code development.
You will use state-of-the-art tools for doing formal verification, code coverage analysis, gate sims, and more.
You will also participate in full chip/sub-system and emulation testing – which gives you exposure to the entire functionality of the chip/system.
You get to participate in ASIC validation in the lab if you are passionate about making the chip come alive.
You will mentor interns and new college graduates.
On a need basis, you will build automation and enhance existing DV methodologies for improving efficiencies.
Required and Desired Skills:
Bachelor’s degree required (Master’s strongly desired) in Electrical Engineering or Computer Science/Engineering with 7+ years' experience.
Strong analytical/ problem solving skills.
Experience in constrained-random verification with methodologies such as UVM is required – Should have developed block level/full-chip test benches from scratch using system Verilog/UVM in prior work.
Experience using emulation systems is a plus.
Knowledge of Computer Architecture/networking protocols and machine learning through previous work is a plus but not required.
Knowledge of Perl/Python/C/C++.
Excellent written and verbal communications skills is necessary.
Demonstrated leadership skills (as verification lead for subsystem or full chip in prior work) is required.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Job Type: Full-time
Pay: $108,750.00 - $257,600.00 per year
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Flexible schedule
- Flexible spending account
- Health insurance
- Health savings account
- Life insurance
- Paid time off
- Parental leave
- Referral program
- Relocation assistance
- Retirement plan
- Tuition reimbursement
- Vision insurance
Schedule:
- Monday to Friday
Ability to commute/relocate:
- Sunnyvale, CA 94089: Reliably commute or willing to relocate with an employer-provided relocation package (Required)
Experience:
- ASIC: 7 years (Required)
- Verification: 7 years (Required)
- SystemVerilog: 7 years (Required)
Work Location: Hybrid remote in Sunnyvale, CA 94089
