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Are you a recently graduated enthusiastic engineer and highly passionate about your career?

Then you belong with us!

CEVA is looking for you to join our growing VLSI team.

Here in CEVA we are developing state of the art DSP ASIC projects in A.I, Vision, Wireless and Base-stations area. The VLSI team is responsible for the planning and the implementation of DSP cores and accelerators which are a part of many future products.

Responsibilities

• Writing block level/micro-architect specifications of modules
• Designing digital logic for IP blocks using HDLs like System Verilog and Verilog
• Verification of sub-systems using variety of tools and methodologies

Essential Criteria:

• a minimum 2.1 Honours degree or higher in electronics
• Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
• Able to travel to customer sites and other CEVA sites

Desirable Criteria:

• Experience in RTL or GTL design flow with tools such as Synopsys, Cadence, ModelSim, etc
• SystemVerilog, Verilog or VHDL (at least one of these), python(optional)