Job description
Summary
Key Qualifications
- Previous exposure to complex IP design
- Understanding of implementing modern design techniques.
- Exposure to energy-efficient & low-power logic design.
- Understanding of logic optimisation, synthesis, timing analysis.
- Fluency with RTL Verilog/VHDL syntax and hardware modelling.
- Familiarity with logic simulation and debug environments as well as formal verification.
- Ability to work well in a team and be productive under tight schedules.
- Excellent communications skills, self-motivated and well-organised.
Description
Education & Experience
Additional Requirements
- Some international travel required.