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Job description

Role: RTL Design Engineer/ ASIC

Location: Menlo Park, CA _ Onsite work only

Hire Type: Full-Time or Contract

Keywords to search:

RTL, Data path, Design, DMA, Control Path, FSMs, Sync Reset, QA sign-off, CDC, LINT, LEC, Clock Gating, Low power, ASIC Design, Architecture.

• More than 8+ Yrs of Front Design experience and methodology
• Strong knowledge of IC chip design methodology, Experience in Data path, Control Path, DMA Design, and Integrations.
• Sound knowledge of RTL design and front-end design tools and flows.
• Good experience in Synthesis, Constraint Development, Linting, and CDC.
• Good communication skills to work in a cross-functional international team with analog, digital and software design engineers.
• The design engineer should architect the digital subsystem together with the system designer.
• Construction of module test cases and performing basic verification of the IP developed.
• Perform synthesis, constraints development, LINT, and CDC check

Job Types: Full-time, Contract

Salary: $76,191.69 - $160,000.00 per year

Benefits:

• Dental insurance

Schedule:

• 8 hour shift

Ability to commute/relocate:

• Menlo Park, CA: Reliably commute or planning to relocate before starting work (Required)

Willingness to travel:

• 25% (Preferred)

Work Location: In person